First, a related-art semiconductor device is described. FIG. 2 is a plan view of the related-art semiconductor device.
In general, an NMOS transistor is used for an ESD protection circuit for protecting an internal circuit from ESD. The pattern of the NMOS transistor is laid out as illustrated in FIG. 2, for example.
An NMOS transistor 90 includes a plurality of sources and a plurality of drains that are alternately formed, a plurality of even-numbered channels formed between the respective sources and the respective drains, and a gate 98 formed above the respective channels. The gate 98 is a multi-finger gate, and is formed of one polysilicon. Each source is connected to a source wiring 99, and each drain is connected to a drain wiring 97. The drain wiring 97 is extended to be connected to a pad 80 (see, for example, Patent Literature 1).